Intel Cyclone 10 GX User Manual page 96

Table 86. TX PMA Parameters
TX channel bonding mode
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port
tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable rx_seriallpbken port
Table 87. RX PMA Parameters
Number of CDR reference Clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port
rx_pma_div_clkout division factor
Enable rx_pma_iqtxrx_clkout port
Enable rx_pma_clkslip port
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
Table 88. Standard PCS Parameters
Standard PCS / PMA interface width
FPGA fabric / Standard TX PCS interface width
FPGA fabric / Standard RX PCS interface width
Enable Standard PCS low latency mode
TX FIFO mode
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Intel Cyclone 10 GX Transceiver PHY User Guide
96
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Parameter
Parameter
Parameters
UG-20070 | 2018.09.24
Value
Not bonded
1, 2, 4, 8
1, 2, 3, 4
0 to 3
On/Off
On/Off
Disabled, 1, 2, 33, 40, 66
On/Off
On/Off
Value
1 to 5
0 to 4
Select legal range defined by the Quartus Prime
software
100, 300, 500, 1000
manual
On/Off
On/Off
Disabled, 1, 2, 33, 40, 66
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Value
10
8
8
Off
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
continued...
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