Model 2: Acknowledgment Model - Intel Cyclone 10 GX User Manual

Figure 154. Dynamic Reconfiguration of Receiver Channel During Device Operation
Device Power Up
rx_analogreset
rx_is_lockedtodata

4.3.2. Model 2: Acknowledgment Model

The acknowledgment model uses an event-driven mechanism. It is used for
applications with strict timing requirements. Instead of waiting for a minimum
assertion time of 70 μs for
to receive the acknowledgment from the Transceiver Native PHY IP core to ensure
successful assertion and deassertion of the analog resets.
To enable the acknowledgment model, enable the following ports in the Transceiver
Native PHY IP core:
•
Enable the
Figure 155. Enabling the tx_analog_reset_ack Port
•
Enable the
Figure 156. Enabling the rx_analog_reset_ack Port
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
254
rx_cal_busy
rx_digitalreset
t = 70 μs
1
req
tx_analogreset
tx_analog_reset_ack
rx_analog_reset_ack
Legal
Reconfiguration
t
Window
req
2 3
and
rx_analogreset
port in the TX PMA
port in the RX PMA
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
t min 4 μs
LTD
4 5
, you must wait
Send Feedback