Intel Cyclone 10 GX User Manual page 334

Table 178. Register Map for Switching Transmitter PLLs
Transceiver Native PHY
Port
tx_serial_clk0
tx_serial_clk1
tx_serial_clk2
tx_serial_clk3
N/A
When performing a PLL switch, you must specify the lookup register address and bit
values you want to switch to. The following procedure describes selection of a specific
transmitter PLL when more than one PLL is connected to a channel. To change the
data rate of the CDR, follow the detailed steps for reconfiguring channel and PLL
blocks. After determining the logical PLL to switch to, follow this procedure to switch
to the desired transmitter PLL:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the appropriate lookup register address (refer to
334) and save the required 4-bit pattern. For example, switching to logical
requires saving bits [7:4] of address 0x117.
3. Encode the 4-bit value read in the previous step into an 8-bit value according to
the following table:
Table 179. Logical PLL Encoding
4-bit Logical PLL Bits
[3..0]
[7..4]
Note: For example, if reconfiguring to logical
4. Perform a read-modify-write to bits[7:0] of address 0x111 using the encoded 8-bit
value.
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
Steps to Perform Dynamic Reconfiguration
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
334
Description
Represents logical . Lookup register
PLL0
stores the mapping from logical
PLL.
Represents logical . Lookup register
PLL1
stores the mapping from logical
PLL.
Represents logical . Lookup register
PLL2
stores the mapping from logical
PLL.
Represents logical . Lookup register
PLL3
stores the mapping from logical
PLL.
PLL selection MUX
{~logical_PLL_offset_readdata[3],
logical_PLL_offset_readdata[1:0],logical_PLL_offset_readdata[3],
logical_PLL_offset_readdata[3:0] }
{~logical_PLL_offset_readdata[7],
logical_PLL_offset_readdata[5:4],logical_PLL_offset_readdata[7],
logical_PLL_offset_readdata[7:4] }
an 8-bit value {~bit[7], bit[5:4], bit[7], bit[7:4]}.
6. Reconfiguration Interface and Dynamic Reconfiguration
0x117 (Lookup Register)
x117[3:0]
to the physical
PLL0
0x117 (Lookup Register)
x117[7:4]
to the physical
PLL1
0x118 (Lookup Register)
x118[3:0]
to the physical
PLL2
0x118 (Lookup Register)
x118[7:4]
to the physical
PLL3
0x111
8-bit Mapping to Address 0x111
then bits [7:4] are encoded to
PLL1
on page 328
UG-20070 | 2018.09.24
Address Bits
[3:0]
[7:4]
[3:0]
[7:4]
[7:0]
Table 178 on page
PLL1
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