Intel Cyclone 10 GX User Manual page 120

2.6.3.5.4. Status Signals
Table 112. Status Signals
Signal Name
led_an
rx_block_lock
2.6.3.5.5. Serial Interface Signals
The serial interface connects to an external device.
Table 113. Serial Interface Signals
Signal Name
tx_serial_data
rx_serial_data
2.6.3.5.6. Transceiver Status and Reconfiguration Signals
Table 114. Control and Status Signals
Signal Name
rx_is_lockedtodata
tx_cal_busy
rx_cal_busy
Transceiver reconfiguration signals for Cyclone 10 GX devices
reconfig_clk
reconfig_reset
reconfig_address
reconfig_write
reconfig_read
reconfig_writedata
reconfig_readdata
reconfig_waitrequest
2.6.3.5.7. Avalon-MM Interface Signals
The Avalon-MM interface is an Avalon-MM slave port. This interface uses word
addressing and provides access to the 16-bit configuration registers of the PHY.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
120
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Direction Clock
Domain
Output Synchronous
to
rx_clkout
Output Synchronous
to
rx_clkout
Direction Width
Output 1
Input 1
Direction Width
Output 1
Output 1
Output 1
Input 1
Input 1
Input 10
Input 1
Input 1
Input 32
Output 32
Output 1
Width Description
1 Asserted when auto-negotiation is
completed.
1 Asserted when the link synchronization for
10GbE is successful.
Description
TX data.
RX data.
Description
Asserted when the CDR is locked to the RX data.
Asserted when TX calibration is in progress.
Asserted when RX calibration is in progress.
Reconfiguration signals connected to the
reconfiguration block. The
provides the timing reference for this interface.
UG-20070 | 2018.09.24
signal
reconfig_clk
Send Feedback