Intel Cyclone 10 GX User Manual page 141

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Port
pipe_rx_polarity[(N-1):
0]
pipe_powerdown[(2N-1):
0]
pipe_tx_margin[(3N-1):
0]
pipe_tx_swing[(N-1):0]
pipe_tx_deemph[(N-1):0]
pipe_rx_eidleinfersel[(
3N-1):0]
pipe_rate[1:0]
Send Feedback
Direction Clock Domain
In Asynchronous
In
tx_coreclkin
In
tx_coreclkin
In
tx_coreclkin
In Asynchronous
In Asynchronous
In Asynchronous
Description
When 1'b1, instructs the PHY layer to invert
the polarity on the received data.
Active High
Requests the PHY to change its power state
to the specified state. The Power States are
encoded as follows:
2'b00: P0 - Normal operation.
2'b01: P0s - Low recovery time, power
saving state.
2'b10: P1 - Longer recovery time, lower
power state .
2'b11: P2 - Lowest power state.
Transmit V margin selection. The PHY-MAC
OD
sets the value for this signal based on the
value from the Link Control 2 Register. The
following encodings are defined:
3'b000: Normal operating range
3'b001: Full swing: 800 - 1200 mV; Half
swing: 400 - 700 mV.
3'b010:-3'b011: Reserved.
3'b100-3'b111: Full swing: 200 - 400mV;
Half swing: 100 - 200 mV else reserved.
Indicates whether the transceiver is using
Full swing or Half swing voltage as defined by
the .
pipe_tx_margin
1'b0-Full swing.
1'b1-Half swing.
Transmit de-emphasis selection. In PCI
Express Gen2 (5 Gbps) mode it selects the
transmitter de-emphasis:
1'b0: –6 dB.
1'b1: –3.5 dB.
When asserted high, the electrical idle state
is inferred instead of being identified using
analog circuitry to detect a device at the
other end of the link. The following encodings
are defined:
3'b0xx: Electrical Idle Inference not required
in current LTSSM state.
3'b100: Absence of COM/SKP OS in 128 ms.
3'b101: Absence of TS1/TS2 OS in 1280 UI
interval for Gen1 or Gen2.
3'b110: Absence of Electrical Idle Exit in
2000 UI interval for Gen1 and 16000 UI
interval for Gen2.
3'b111: Absence of Electrical Idle exit in 128
ms window for Gen1.
Note: Recommended to implement Receiver
Electrical Idle Inference (EII) in FPGA
fabric.
The 2-bit encodings defined in the following
list:
2'b00: Gen1 rate (2.5 Gbps)
2'b01: Gen2 rate (5.0 Gbps)
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
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