Implementing Protocols In Intel Cyclone 10 Gx Transceivers; Transceiver Design Ip Blocks - Intel Cyclone 10 GX User Manual

UG-20070 | 2018.09.24
Send Feedback
2. Implementing Protocols in Intel Cyclone 10 GX
Transceivers

2.1. Transceiver Design IP Blocks

Note: Intel Cyclone 10 GX only supported with Intel Quartus Prime Pro Edition 17.1 and
future versions.
Figure 7. Cyclone 10 GX Transceiver Design Fundamental Building Blocks
Reset controller is used for resetting the
transceiver channels.
Transceiver PLL IP core provides a clock source
to clock networks that drive the transceiver
channels. In Cyclone 10 devices, PLL IP Core
is separate from the transceiver PHY IP core.
Avalon master allows access to Avalon-MM
reconfiguration registers via the Avalon
Memory Mapped interface. It enables PCS,
PMA , and PLL reconfiguration. To access
the reconfiguration registers, implement an
Avalon master in the FPGA fabric. This faciliates
reconfiguration by performing reads and writes
through the Avalon-MM interface.
This block can be either a MAC IP core, or
a frame generator / analyzer or a
data generator / analyzer.
Note:
(1) The Transceiver PHY IP core can be one of the supported PHY IP Cores ( For example: Native PHY IP Core).
(2) You can either design your own reset controller or use the Transceiver PHY Reset Controller.
Legend:
Intel generated IP block
User created IP block
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
Analog and Digital
Reset Bus
Transceiver PHY
Reset Controller (2)
Transceiver Master/Local
PLL IP Core
Clock
Generation
Non-Bonded and
Block
Bonded Clocks
Avalon-MM
Interface
Avalon-MM Master
MAC IP Core / Parallel Data Bus
Data Generator /
Data Analyzer
Reset Ports
Transceiver PHY IP core controls the PCS and
PMA configurations and transceiver
channels functions for all communication
(1)
Transceiver PHY IP Core
protocols.
Reconfiguration
Registers
ISO
9001:2015
Registered