Intel Cyclone 10 GX User Manual page 109

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
2.6.3.1.1. Features
Table 100. PHY Features
Feature
Multiple operating speeds
MAC-side interface
Network-side interface
®
Avalon Memory-Mapped (Avalon-MM)
interface
PCS function
Auto-negotiation
Sync-E
2.6.3.1.2. Release Information
Table 101. PHY Release Information
Release Date
Ordering Codes
Open Core Plus
2.6.3.1.3. Device Family Support
Table 102. Intel FPGA IP Core Device Support Levels
Device Support Level
Preliminary
Final
Device Family
Intel Cyclone 10 GX
2.6.3.1.4. Resource Utilization
The following estimates are obtained by compiling the PHY IP core with the Intel
Quartus Prime software.
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10M, 100M, 1G, 2.5G, 5G, and 10G.
32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII).
10.3125 Gbps for 10M/100M/1G/2.5G/5G/10G (USXGMII).
Provides access to the configuration registers of the PHY.
USXGMII PCS for 10M/100M/1G/2.5G/5G/10G.
USXGMII Auto-negotiation supported in the 10M/100M/1G/2.5G/5G/10G
(USXGMII) configuration.
Provides the clock for Sync-E implementation.
Item
Version
Product ID
Vendor ID
Intel verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing
timing analysis for the device family. This IP core can be used in production
designs with caution.
Intel verifies the IP core with final timing models for this device family. The IP
core meets all functional and timing requirements for the device family. This IP
core is ready to be used in production designs.
Operating Mode
10M/100M/1G/2.5G/5G/10G
Description
Description
18.1
September 2018
IP-10GMRPHY
00E4
6AF7
Supported
Definition
Support Level
Final
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
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