Intel Cyclone 10 GX User Manual page 75

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
required by the protocol. Based on these FIFO status and control signals, you can
implement the multi-lane deskew alignment state machine in the FPGA fabric to
control the transceiver RX FIFO block.
Note: You must also implement the soft bonding logic to control the transceiver TX FIFO
block.
2.5.2.2.1. TX FIFO Soft Bonding
The MAC layer logic and TX soft bonding logic control the writing of the Interlaken
word to the TX FIFO with
by monitoring the TX FIFO flags (
tx_fifo_empty
enable is controlled by the frame generator. If
high, the frame generator reads data from the TX FIFO.
A TX FIFO pre-fill stage must be implemented to perform the TX channel soft bonding.
The following figure shows the state of the pre-fill process.
Send Feedback
tx_enh_data_valid
tx_fifo_full
, , and so forth). On the TX FIFO read side, a read
tx_fifo_pempty
(functions as a TX FIFO write enable)
, ,
tx_fifo_pfull
tx_enh_frame_burst_en
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
is asserted
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