2.5G/5G/10G Multi-Rate Ethernet Phy Intel Fpga Ip Core - Intel Cyclone 10 GX User Manual

2.6.3. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core
2.6.3.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core
The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP core implements the
Ethernet protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard. The PHY
IP core consists of a physical coding sublayer (PCS) function and an embedded
physical media attachment (PMA). You can dynamically switch the PHY operating
speed.
Note: Intel FPGAs implement and support the required Media Access Control (MAC) and PHY
(PCS+PMA) IP to interface in a chip-to-chip or chip-to-module channel with external
MGBASE-T and NBASE-T PHY standard devices. You are required to use an external
PHY device to drive any copper media.
Figure 54. Block Diagram of the PHY IP Core
Intel Device with Serial Transceivers
LL Ethernet
10G MAC
User
Application
Legend
Related Information
• Using the Cyclone 10 GX Transceiver Native PHY IP Core
• Recommended Reset Sequence
• Low Latency Ethernet 10G MAC Intel FPGA IP User Guide
Describes the Low Latency Ethernet 10G MAC Intel FPGA IP core.
• Low Latency Ethernet 10G MAC Intel Cyclone 10 GX FPGA IP Design Example User
Guide
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
108
1G/2.5G/5G/10G Multi-rate Ethernet PHY
TX
XGMII
Soft PCS
RX
XGMII
Configuration
Registers
Avalon-MM
Interface
Transceiver
Hard IP
Reset
Soft Logic Controller
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Native PHY Hard IP
Hard PCS PMA
PLL
for 10 GbE
322-MHz
Reference Clock
on page 246
UG-20070 | 2018.09.24
TX Serial
External
PHY
RX Serial
on page 26
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