Enhanced Pcs Parameters - Intel Cyclone 10 GX User Manual

Parameters
Enable rx_pma_clkslip
port
Enable
rx_is_lockedtodata
port
Enable
rx_is_lockedtoref port
Enable
rx_set_lockedtodata
port and
rx_set_lockedtoref
ports
Enable rx_seriallpbken
port
Enable PRBS (Pseudo
Random Bit Sequence)
verifier control and
status port

2.4.4. Enhanced PCS Parameters

This section defines parameters available in the Native PHY IP core GUI to customize
the individual blocks in the Enhanced PCS.
The following tables describe the available parameters. Based on the selection of the
Transceiver Configuration Rule , if the specified settings violate the protocol
standard, the Native PHY IP core Parameter Editor prints error or warning
messages.
Note: For detailed descriptions about the optional ports that you can enable or disable, refer
to the Enhanced PCS Ports section.
Table 12. Enhanced PCS Parameters
Parameter
Enhanced PCS / PMA
interface width
FPGA fabric /Enhanced
PCS interface width
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
34
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Value
On/Off
Enables the optional
edge on this signal causes the RX serializer to slip the serial data
by one clock cycle, or 2 unit intervals (UI).
On/Off
Enables the optional
This signal indicates that the RX CDR is currently in lock to data
mode or is attempting to lock to the incoming data stream. This is
an asynchronous output signal.
On/Off
Enables the optional
This signal indicates that the RX CDR is currently locked to the
CDR reference clock. This is an asynchronous output signal.
On/Off Enables the optional
rx_set_lockedtoref
control ports to manually control the lock mode of the RX CDR.
These are asynchronous input signals.
On/Off
Enables the optional
assertion of this signal enables the TX to RX serial loopback path
within the transceiver. This is an asynchronous input signal.
On/Off
Enables the optional
rx_prbs_done
status from the internal PRBS verifier.
Range
32, 40, 64 Specifies the interface width between the Enhanced PCS and the
PMA.
32, 40, 64, 66, 67 Specifies the interface width between the Enhanced PCS and the
FPGA fabric.
The 66-bit FPGA fabric to PCS interface width uses 64-bits from the
TX and RX parallel data. The block synchronizer determines the
block boundary of the 66-bit word, with lower 2 bits from the
control bus.
UG-20070 | 2018.09.24
Description
control input port. A rising
rx_pma_clkslip
status output port.
rx_is_lockedtodata
status output port.
rx_is_lockedtoref
rx_set_lockedtodata
control input ports. You can use these
control input port. The
rx_seriallpbken
,
rx_prbs_err rx_prbs_clr
control ports. These ports control and collect
Description
and
, and
continued...
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