Intel Cyclone 10 GX User Manual page 320

You can optionally allow the Native PHY IP core to include PMA Analog settings in the
configuration files by enabling the feature Include PMA Analog settings in
configuration files in the Dynamic Reconfirmation tab of the Transceiver Native
PHY IP Parameter Editor. This feature is disabled by default. Enabling this feature adds
the PMA analog settings specified in the Analog PMA settings (Optional) tab of the
Native PHY IP Parameter Editor to the configuration files. Even with this option
enabled in the Native PHY IP Parameter Editor, you must still specify Quartus Settings
File (QSF) assignments for your analog settings when compiling your static design.
The analog settings selected in the Native PHY IP Parameter Editor are used only to
include these settings and their dependent settings in the selected configuration files.
Refer to the Analog Parameter Settings chapter for details about QSF assignments for
the analog settings.
Example 2. SystemVerilog Configuration File
26'h008FF04,
// [25:16]-DPRIO address=0x008;
// [15:8]-bit mask=0xFF;
// [7:7]- hssi_tx_pcs_pma_interface_pldif_datawidth_mode=pldif_data_10bit(1'h0);
// [6:5]-hssi_tx_pcs_pma_interface_tx_pma_data_sel=ten_g_pcs(2'h0);
// [4:4]-hssi_tx_pcs_pma_interface_prbs_gen_pat=prbs_gen_dis(1'h0);
// [3:0]-hssi_tx_pcs_pma_interface_sq_wave_num=sq_wave_default(4'h4);
...
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_VALUE = "pldif_data_10bit";
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_OFST = 8;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_OFST = 7;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_HIGH = 7;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_SIZE = 1;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_BITMASK =
32'h00000080;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALMASK =
32'h00000000;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALUE = 1'h0;
The SystemVerilog configuration files contain two parts. The first part consists of a
data array of 26-bit hexadecimal values. The second part consists of parameter
values. For the data array, each 26-bit hexadecimal value is associated with a
comment that describes the various bit positions.
Table 175. Mapping of SystemVerilog Configuration File Line
Bit Position
[25:16] The channel or PLL address.
[15:8] The channel or PLL bit mask. The bit mask exposes the bits that are configured in either the Transceiver
Native PHY or the transmit PLL IP cores.
[7:0] Feature bit values.
For example, a value of 26'h008FF04 represents an address of 0x008 and a bit mask
of 0xFF. The four features that reside at address 0x008 are:
•
hssi_tx_pcs_pma_interface_pldif_datawidth_mode
•
hssi_tx_pcs_pma_interface_tx_pma_data_sel
•
hssi_tx_pcs_pma_interface_prbs_gen_pat
•
hssi_tx_pcs_pma_interface_sq_wave_num
Writing to bit 7 of address 0x008 changes the
hssi_tx_pcs_pma_interface_pldif_datawidth_mode
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
320
6. Reconfiguration Interface and Dynamic Reconfiguration
Description
with a value of 1'h0
with a value of 4'h4
UG-20070 | 2018.09.24
with a value of 1'h0
with a value of 2'h0
feature.
Send Feedback