Intel Cyclone 10 GX User Manual page 5

Contents
6.2.1. Reading from the Reconfiguration Interface............................................... 318
6.2.2. Writing to the Reconfiguration Interface.................................................... 318
6.3. Configuration Files............................................................................................. 319
6.4. Multiple Reconfiguration Profiles........................................................................... 321
6.5. Embedded Reconfiguration Streamer.................................................................... 322
6.6. Arbitration.........................................................................................................325
6.7. Recommendations for Dynamic Reconfiguration......................................................327
6.8. Steps to Perform Dynamic Reconfiguration............................................................ 328
6.9. Direct Reconfiguration Flow................................................................................. 330
6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow..................................... 331
6.11. Reconfiguration Flow for Special Cases................................................................ 333
6.11.1. Switching Transmitter PLL ....................................................................333
6.11.2. Switching Reference Clocks....................................................................335
6.12. Changing PMA Analog Parameters......................................................................338
6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow................. 341
6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow.. 342
6.12.3. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow... 343
6.13. Ports and Parameters........................................................................................346
6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks...................... 351
6.15. Embedded Debug Features................................................................................ 353
6.15.1. Altera Debug Master Endpoint................................................................ 354
6.15.2. Optional Reconfiguration Logic............................................................... 354
6.16. Using Data Pattern Generators and Checkers....................................................... 359
6.16.1. Using PRBS Data Pattern Generator and Checker..................................... 359
6.16.2. Using Pseudo Random Pattern Mode........................................................368
6.17. Timing Closure Recommendations...................................................................... 369
6.18. Unsupported Features....................................................................................... 371
6.19. Cyclone 10 GX Transceiver Register Map.............................................................372
6.20. Reconfiguration Interface and Dynamic Reconfiguration Revision History..................372
7. Calibration.................................................................................................................. 373
7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine .................373
7.2. Calibration Registers...........................................................................................375
7.2.1. Avalon-MM Interface Arbitration Registers................................................. 375
7.2.2. Transceiver Channel Calibration Registers.................................................. 376
7.2.3. Fractional PLL Calibration Registers...........................................................376
7.2.4. ATX PLL Calibration Registers...................................................................377
7.2.5. Capability Registers................................................................................ 377
7.2.6. Rate Switch Flag Register........................................................................ 379
7.3. Power-up Calibration.......................................................................................... 380
7.4. User Recalibration.............................................................................................. 383
7.4.1. Conditions That Require User Recalibration................................................ 383
7.4.2. User Recalibration Sequence ................................................................... 384
7.5. Calibration Example............................................................................................385
7.5.1. ATX PLL Recalibration............................................................................. 385
7.5.2. Fractional PLL Recalibration..................................................................... 385
7.5.3. CDR/CMU PLL Recalibration..................................................................... 386
7.5.4. PMA Recalibration...................................................................................386
7.6. Calibration Revision History................................................................................. 387
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Intel Cyclone 10 GX Transceiver PHY User Guide
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