Ip Core File Locations - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Name
tx_polinv[<n>-1:0]
rx_polinv[<n>-1:0]
rx_std_signaldetect[<n
>-1:0]

2.4.11. IP Core File Locations

When you generate your Transceiver Native PHY IP, the Quartus
generates the HDL files that define your instance of the IP. In addition, the Quartus
Prime software generates an example Tcl script to compile and simulate your design in
the ModelSim simulator. It also generates simulation scripts for Synopsys VCS, Aldec
Active-HDL, Aldec Riviera-Pro, and Cadence Incisive Enterprise.
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Direction Clock Domain
Input Asynchronous
Input Asynchronous
Output Asynchronous
Description
receive circuitry receives all words in the reverse order. The
bit reversal circuitry operates on the output of the word
aligner.
When asserted, the TX polarity bit is inverted. Only active
when TX bit polarity inversion is enabled.
When asserted, the RX polarity bit is inverted. Only active
when RX bit polarity inversion is enabled.
When enabled, the signal threshold detection circuitry
senses whether the signal level present at the RX input
buffer is above the signal detect threshold voltage. You can
specify the signal detect threshold using a Quartus Prime
Settings File (.qsf) assignment. This signal is required for
the PCI Express, SATA and SAS protocols.
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Intel Cyclone 10 GX Transceiver PHY User Guide
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Prime software
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