Intel Cyclone 10 GX User Manual page 355

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
Address
0x211[7:0]
0x212[7:0]
0x213[0]
The following capability registers are available for the PLL IP cores.
Table 196. Capability Registers for the PLL IP Cores
Address
0x200[7:0]
0x204[0]
0x205[0]
0x210[7:0]
6.15.2.2. Control and Status Registers
Control and status registers are optional registers that memory-map some of the
status outputs from and control inputs to the Native PHY and PLL.
The following control and status registers are available for the Native PHY IP core.
Table 197. Control Registers for the Native PHY IP Core
Address
0x2E0[0]
0x2E0[1]
0x2E0[2]
0x2E0[3]
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Type Name
RO Channel Number
RO Duplex
RO PRBS Soft Enabled
Type Name
RO IP Identifier
RO Status Register Enabled
RO Control Register Enabled
RO Master CGB Enabled
Type Register
RW
set_rx_locktodata
RW
set_rx_locktoref
RW
override_set_rx_loc
ktodata
RW
override_set_rx_loc
ktoref
Description
Shows the unique channel number.
Shows the transceiver mode:
• 2'b00 = Unused
• 2'b01 = TX
• 2'b10 = RX
• 2'b11 = Duplex
Indicates whether the PRBS soft accumulators are
enabled. 1'b1 indicates the accumulators are
enabled.
Description
Unique identifier for the PLL IP instance.
Indicates if the status registers have been enabled or
not. 1'b1 indicates that the status registers have
been enabled.
Indicates if the control registers have been enabled
or not. 1'b1 indicates that the control registers have
been enabled.
Indicates if the Master Clock Generation Block has
been enabled. 1'b1 indicates the master CGB is
enabled.
Description
Asserts the
set_rx_locktodata
receiver. 1'b1 sets the ADME
set_rx_locktodata
register. See
override_set_rx_locktodata
Asserts the
set_rx_locktoref
receiver. 1'b1 sets the ADME
set_rx_locktoref
register. See
override_set_rx_locktoref
below.
Selects whether the receiver listens to the ADME
register or the
set_rx_locktodata
port. 1'b1 indicates that the
rx_set_locktodata
receiver listens to the ADME
set_rx_locktodata
register.
Selects whether the receiver is listens to the AMDE
register or the
set_rx_locktoref
port. 1'b1 indicates that the
rx_set_locktoref
receiver listens to the ADME
set_rx_locktoref
register.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
signal to the
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