Intel Cyclone 10 GX User Manual page 234

Figure 140. PHY IP Core and PLL IP Core Connection for Multi-Channel xN Non-Bonded
Configuration
In this example, the same PLL is used to drive 10 channels across two transceiver banks.
Steps to implement a multi-channel xN non-bonded configuration
1. You can use either the ATX PLL or fPLL for multi-channel xN non-bonded
configuration.
• Because the CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL
can be used for this example.
2. Configure the PLL IP core using the IP Parameter Editor. Enable Include
Master Clock Generation Block .
3. Configure the Native PHY IP core using the IP Parameter Editor
• Set the Native PHY IP core TX Channel bonding mode to Non-Bonded .
• Set the number of channels as per your design requirement. In this example,
the number of channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
234
Transceiver PLL
Instance (5 GHz)
x1 x6
Master
ATX PLL
CGB
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
xN
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
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