Intel Cyclone 10 Gx Transceiver Phy Overview Revision History - Intel Cyclone 10 GX User Manual

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1. Intel Cyclone 10 GX Transceiver PHY Overview
UG-20070 | 2018.09.24

1.4. Intel Cyclone 10 GX Transceiver PHY Overview Revision History

Document
Version
2017.12.28 Made the following changes:
• Updated the "Intel Cyclone 10 GX Default Settings Preset" Figure.
• Changed the transceiver count back to 6 for 10CX085 package F672 in the "Package Details for
Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device"
table.
2017.11.06 Made the following changes:
• Changed the description of the ATX PLL in the "Advanced Transmit (ATX) PLL" section.
• Changed the transceiver counts for the F672 package in the "Package Details for Devices with
Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device" table.
• Changed the description of the Fractional PLL in the "Fractional PLL (fPLL)" section.
• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 12 Transceiver
Channels and One PCIe Hard IP Block" figure.
• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 10 Transceiver
Channels and One PCIe Hard IP Block" figure.
• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 6 Transceiver
Channels and One PCIe Hard IP Block" figure.
2017.05.08 Initial release.
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Intel Cyclone 10 GX Transceiver PHY User Guide
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