Intel Cyclone 10 GX User Manual page 252

Figure 152. Resetting the Transceiver Channel During Device Operation
rx_is_lockedtodata
4.3.1.1.4. Dynamic Reconfiguration of Channel Using the Default Model
TX Channel
The numbers in this list correspond to the numbers in the following figure.
1. Assert
pll_cal_busy
2. Perform dynamic reconfiguration after minimum 70 μs of asserting
tx_analogreset
3. Deassert
Deassert
deassert
4. The
pll_locked
minimum 70 μs after deasserting
signal.
5. Deassert
tx_digitalreset
duration after
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
252
Device Power Up
pll_cal_busy
tx_cal_busy
rx_cal_busy
tx_analogreset
pll_powerdown
pll_locked
tx_digitalreset
rx_analogreset
rx_digitalreset
1
t = 70 μs
req
,
tx_analogreset pll_powerdown
and
tx_cal_busy
.
after performing a dynamic reconfiguration.
pll_powerdown
. This step can be done at the same time or after you
tx_analogreset
.
pll_powerdown
signal goes high after the TX PLL acquires lock. Wait for
tx_digitalreset
signal must stay asserted for a minimum
tx_analogreset
t t
req req
t
min 70 μs
rx_digitalreset
2 3
, and
tx_digitalreset
are low.
tx_analogreset
after goes high. The
pll_locked
is deasserted.
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
t min 4 μs
4
LTD
5 6
, while
to monitor the
pll_locked
t
tx_digitalreset
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