Intel Cyclone 10 GX User Manual page 180

2.9.2.14. TX Bit Reversal
The TX bit reversal feature can be enabled in low latency, basic, and basic rate match
mode. The word aligner is available in any mode. This feature is parameter-based, and
creates no additional ports. If there is more than one channel in the design, all
channels have TX bit reversal.
To enable TX bit reversal, select the Enable TX bit reversal option in Platform
Designer. It can also be dynamically controlled with dynamic reconfiguration.
Figure 110. TX Bit Reversal
2.9.2.15. TX Byte Reversal
The TX byte reversal feature can be enabled in low latency, basic, and basic rate
match mode. The word aligner is available in any mode. This feature is parameter-
based, and creates no additional ports. If there is more than one channel in the
design, all channels have TX byte reversal.
To enable TX byte reversal, select the Enable TX byte reversal option in Platform
Designer. It can also be dynamically controlled with dynamic reconfiguration.
Figure 111. TX Byte Reversal
2.9.2.16. How to Implement the Basic, Basic with Rate Match Transceiver
Configuration Rules in Cyclone 10 GX Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture,
and the reset controller before implementing your Basic protocol IP.
1. Open the IP Catalog and select the Native PHY IP.
Refer to
2. Select Basic/Custom (Standard PCS) or Basic/Custom w/Rate Match
(Standard PCS) from the Transceiver configuration rules list located under
Datapath Options depending on which configuration you want to use.
3. Use the parameter values in the tables in
Settings for the Basic Protocol
presets described in
setting to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
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Intel Cyclone 10 GX Transceiver PHY User Guide
180
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
tx_parallel_data 11111100001110111100
rx_parallel_data 00000...
tx_parallel_data 11111100001110111100
rx_parallel_data 00000000... 11101111001111110000
Select and Instantiate the PHY IP Core
as a starting point. Or, you can use the protocol
Transceiver Native PHY
00111101110000111111
on page 17.
Transceiver Native PHY IP Parameter
Presets. You can then modify the
UG-20070 | 2018.09.24
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