Intel Cyclone 10 GX User Manual page 160

Figure 77. Signals and Ports of Native PHY IP for Basic (Enhanced PCS) Configurations
rx_is_lockedtodata
5. Configure and instantiate the PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7. Connect the Native PHY IP core to the PLL IP core and the reset controller.
Figure 78. Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design
8. Simulate your design to verify its functionality.
2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS)
This section contains the recommended parameter values for this protocol. Refer to
Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of
parameter values.
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Intel Cyclone 10 GX Transceiver PHY User Guide
160
tx_cal_busy
NIOS
rx_cal_busy Hard Calibration IP
TX PMA
tx_serial_data Serializer
Clock
tx_serial_clk0
Generation
(from TX PLL)
Block
RX PMA
Deserializer
rx_serial_data
CDR
rx_cdr_refclk0
rx_is_lockedtoref
rx_cdr_refclk0
Design
32-bit data
Testbench
gearbox ratio)
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
TX Enhanced PCS
tx_parallel_data[127:0]
RX Enhanced PCS
rx_parallel_data[127:0]
PLL IP Core
(32:32
Cyclone 10 Transceiver
Native PHY
UG-20070 | 2018.09.24
reconfig_reset
Reconfiguration
reconfig_clk
Registers
reconfig_avmm
tx_digital_reset tx_digital_reset
tx_control[17:0] tx_control[17:0]
tx_parallel_data[127:0]
tx_coreclkin tx_coreclkin
tx_clkout tx_clkout
tx_enh_data_valid tx_enh_data_valid
tx_analog_reset
rx_analog_reset
rx_digital_reset rx_digital_reset
rx_clkout rx_clkout
rx_coreclkin rx_coreclkin
rx_parallel_data[127:0]
rx_control[19:0] rx_control[19:0]
Reset
Controller
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