Intel Cyclone 10 GX User Manual page 337

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
Transceiver fPLL Port
N/A
pll_refclk0
pll_refclk1
pll_refclk2
pll_refclk3
pll_refclk4
N/A
Specify the logical reference clock and respective address and bits of the replacement
clock when performing a reference clock switch. Follow this procedure to switch to the
selected reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register for MUX 0 and save the required 5-bit pattern. For
example, switching to logical
3. Perform a read-modify-write to bits [4:0] at address 0x114 using the 5-bit value
obtained from the lookup register.
4. Read from the lookup register for MUX 1 and save the required 5-bit pattern. For
example, switching to logical
5. Perform a read-modify-write to bits [4:0] at address 0x11C using the 5-bit value
obtained from the lookup register.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
Steps to Perform Dynamic Reconfiguration
6.11.2.3. CDR and CMU Reference Clock Switching
You can use the reconfiguration interface to specify which reference clock source
drives the CDR and CMU PLL. The CDR and CMU support clocking by up to five
different reference clock sources.
Before initiating a reference clock switch, ensure that your CDR and CMU defines more
than one reference clock source. For the CDR, specify the parameter on the RX PMA
tab during the Native PHY IP parameterization. For the CMU, specify the Number of
PLL reference clocks under the PLL tab when parameterizing the CMU PLL.
Send Feedback
Description
fPLL refclk selection .
MUX_0
Represents logical for
refclk0
register stores the mapping from logical
x11D[4:0]
to the physical refclk for MUX_1.
refclk0
Represents logical for
refclk1
register stores the mapping from logical
x11E[4:0]
to the physical refclk for MUX_1.
refclk1
Represents logical for
refclk2
register stores the mapping from logical
x11F[4:0]
to the physical refclk for MUX_1.
refclk2
Represents logical for
refclk3
register stores the mapping from logical
x120[4:0]
to the physical refclk for MUX_1.
refclk3
Represents logical for
refclk4
register stores the mapping from logical
x121[4:0]
to the physical refclk for MUX_1.
refclk4
fPLL refclk selection .
MUX_1
refclk3
refclk3
0x114
0x11D (Lookup Register)
. Lookup
MUX_1
0x11E (Lookup Register)
. Lookup
MUX_1
. Lookup 0x11F (Lookup Register)
MUX_1
0x120 (Lookup Register)
. Lookup
MUX_1
0x121 (Lookup Register)
. Lookup
MUX_1
0x11C
requires use of bits[4:0] at address 0x11A.
requires use of bits[4:0] at address 0x120.
on page 328
® ®
Intel Cyclone
Address Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
10 GX Transceiver PHY User Guide
337