How To Connect Tx Plls For Pipe Gen1 And Gen2 Modes - Intel Cyclone 10 GX User Manual

2.7.3. How to Connect TX PLLs for PIPE Gen1 and Gen2 Modes

Figure 63. Use fPLL for Gen1/Gen2 x1 Mode
fPLL1
ATX PLL1
Path for Clocking in
Gen1/Gen2 x1 Mode
fPLL0
ATX PLL0
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x1 mode.
2. Gen1/Gen2 x1 mode uses the ATX PLL or fPLL.
3. Gen1/Gen2 x1 can use any channel from the given bank for which the ATX PLL or fPLL is enabled.
4. Connect pll_pcie_clk from either ATX PLL or fPLL to the pipe_hclk_in port on Native PHY.
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Intel Cyclone 10 GX Transceiver PHY User Guide
128
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
X1 Network
Master 4
CGB1
4
Master
CGB0
Ch 5
6
CGB
CDR
Ch 4
6
CGB
CDR
Ch 3
6
CGB
CDR
Ch 2
6
CGB
CDR
Ch 1
6
CGB
CDR
Ch 0
6
CGB
CDR
UG-20070 | 2018.09.24
Path for Clocking in
Gen1/Gen2 x1 Mode
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