Ports And Parameters - Intel Cyclone 10 GX User Manual

6.13. Ports and Parameters

The reconfiguration interface is integrated in the Native PHY instance and the TX PLL
instances. Instantiate the Native PHY and the TX PLL IP cores in Qsys by clicking
Tools
specific parameter editor. To expose the reconfiguration interface ports, select the
Enable dynamic reconfiguration option when parameterizing the IP core.
You can share the reconfiguration interface among all the channels by turning on
Share reconfiguration interface when parameterizing the IP core. When this option
is enabled, the IP core presents a single reconfiguration interface for dynamic
reconfiguration of all channels. Address bits [9:0] provide the register address in the
reconfiguration space of the selected channel. The remaining address bits of the
reconfiguration address specify the selected logical channel. For example, if there are
four channels in the Native PHY IP instance,
address and
channels. For example, 2'b01 in
channel 1.
The following figure shows the signals available when the Native PHY IP core is
configured for four channels and the Share reconfiguration interface option is
enabled.
Figure 217. Signals Available with Shared Native PHY Reconfiguration Interface
Table 191. Reconfiguration Interface Ports with Shared Native PHY Reconfiguration
Interface
The reconfiguration interface ports when Share reconfiguration interface is enabled. <N> represents the
number of channels.
Port Name
reconfig_clk
reconfig_reset
reconfig_write
reconfig_read
reconfig_address[log2<N>+9:0]
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
346
IP Catalog. You can define parameters for IP cores by using the IP core-
reconfig_address[11:10]
reconfig_reset
reconfig_write
reconfig_read
reconfig_address[11:0]
reconfig_writedata[31:0]
reconfig_readdata[31:0]
reconfig_waitrequest
Direction
Input
Input
Input
Input
Input
6. Reconfiguration Interface and Dynamic Reconfiguration
reconfig_address[9:0]
are binary encoded to specify the four
reconfig_address[11:10]
Native PHY IP Core
reconfig_clk clk
reset
write
read
address
writedata
readdata
waitrequest
Clock Domain
N/A Avalon clock. The clock frequency is 100-125
MHz.
Resets the Avalon interface. Asynchronous to
reconfig_clk
assertion and synchronous to deassertion.
Write enable signal. Signal is active high.
reconfig_clk
Read enable signal. Signal is active high.
reconfig_clk
Address bus. The lower 10 bits specify address
reconfig_clk
and the upper bits specify the channel.
UG-20070 | 2018.09.24
specifies the
specifies logical
Description
continued...
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