Intel Cyclone 10 GX User Manual page 4

3.4. Clock Generation Block....................................................................................... 216
3.5. FPGA Fabric-Transceiver Interface Clocking............................................................ 217
3.6. Transmitter Data Path Interface Clocking............................................................... 219
3.7. Receiver Data Path Interface Clocking................................................................... 220
3.8. Unused/Idle Clock Line Requirements................................................................... 221
3.9. Channel Bonding................................................................................................222
3.9.1. PMA Bonding......................................................................................... 222
3.9.2. PMA and PCS Bonding.............................................................................224
3.9.3. Selecting Channel Bonding Schemes......................................................... 225
3.9.4. Skew Calculations.................................................................................. 226
3.10. PLL Feedback and Cascading Clock Network......................................................... 226
3.11. Using PLLs and Clock Networks.......................................................................... 231
3.11.1. Non-bonded Configurations....................................................................231
3.11.2. Bonded Configurations.......................................................................... 235
3.11.3. Implementing PLL Cascading..................................................................240
3.11.4. Timing Closure Recommendations...........................................................241
3.12. PLLs and Clock Networks Revision History............................................................241
4. Resetting Transceiver Channels.................................................................................. 243
4.1. When Is Reset Required? ................................................................................... 243
4.2. Transceiver PHY Implementation.......................................................................... 244
4.3. How Do I Reset?................................................................................................ 245
4.3.1. Model 1: Default Model........................................................................... 245
4.3.2. Model 2: Acknowledgment Model..............................................................254
4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals....................... 258
4.4. Using the Transceiver PHY Reset Controller............................................................ 259
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP............................... 261
4.4.2. Transceiver PHY Reset Controller Parameters............................................. 261
4.4.3. Transceiver PHY Reset Controller Interfaces............................................... 264
4.4.4. Transceiver PHY Reset Controller Resource Utilization.................................. 267
4.5. Using a User-Coded Reset Controller.....................................................................267
4.5.1. User-Coded Reset Controller Signals......................................................... 268
4.6. Combining Status or PLL Lock Signals .................................................................. 269
4.7. Timing Constraints for Bonded PCS and PMA Channels............................................ 269
4.8. Resetting Transceiver Channels Revision History..................................................... 271
5. Cyclone 10 GX Transceiver PHY Architecture............................................................. 272
5.1. Cyclone 10 GX PMA Architecture......................................................................... 272
5.1.1. Transmitter........................................................................................... 272
5.1.2. Receiver................................................................................................275
5.1.3. Loopback.............................................................................................. 282
5.2. Cyclone 10 GX Enhanced PCS Architecture........................................................... 283
5.2.1. Transmitter Datapath.............................................................................284
5.2.2. Receiver Datapath................................................................................. 291
5.3. Cyclone 10 GX Standard PCS Architecture............................................................ 299
5.3.1. Transmitter Datapath..............................................................................300
5.3.2. Receiver Datapath.................................................................................. 305
5.4. Intel Cyclone 10 GX Transceiver PHY Architecture Revision History............................314
6. Reconfiguration Interface and Dynamic Reconfiguration .......................................... 315
6.1. Reconfiguring Channel and PLL Blocks...................................................................315
6.2. Interacting with the Reconfiguration Interface........................................................ 316
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Intel Cyclone 10 GX Transceiver PHY User Guide
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