Recommendations For Dynamic Reconfiguration - Intel Cyclone 10 GX User Manual

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24

6.7. Recommendations for Dynamic Reconfiguration

Recommendations for TX PLLs
Intel recommends you control
in the following cases:
• Reconfiguring fPLL from integer mode to fractional mode
• Reconfiguring fPLL within fractional mode from one rate to another
For all other reconfiguration scenarios, do not hold the PLL in reset before and during
reconfiguration.
When reconfiguring across data rates or protocol modes, Intel recommends that you
hold the channel transmitter (analog and digital) associated with the PLL in reset
during reconfiguration and recalibration of the PLL.You can use the
tx_digitalreset
ports or use the channel soft register for digital and analog resets. For details about
placing the channel in analog reset, refer to the "Model 1: Default Model" and "Model
2: Acknowledgment Model" sections of the Resetting Transceiver Channels chapter.
Note: If you need to reconfigure the ATX PLL, use TX PLL switching mode or use local clock
divider to achieve new data rate to avoid recalibrating the ATX PLL. Refer to "Transmit
PLLs Spacing Guidelines when using ATX PLLs and fPLLs" in the "PLLs and Clock
Networks" chapter for more details.
Recommendations for Channels
• When reconfiguring across data rates or protocol modes, Intel recommends that
you hold the channel transmitter (analog and digital) in reset during
reconfiguration and recalibration of the channel transmitter. You can use the
tx_digitalreset
rx_analogreset
resets. For details about placing the channel in analog reset, refer to the "Model 1:
Default Model" and "Model 2: Acknowledgment Model" sections of the Resetting
Transceiver Channels chapter.
• When reconfiguring across data rates or protocol modes, Intel recommends that
you hold the channel receiver (analog and digital) in reset during reconfiguration
and recalibration of the channel receiver. You can use the
rx_digitalreset
channel soft register for digital and analog resets. For details about placing the
channel in analog reset, refer to the "Model 1: Default Model" and "Model 2:
Acknowledgment Model" sections of the Resetting Transceiver Channels chapter.
• When performing reconfiguration on channels not involving data rate or protocol
mode change, Intel recommends that you hold the channel transmitter (digital
only) in reset during reconfiguration.
• When performing reconfiguration on channels not involving data rate or protocol
mode change, Intel recommends that you hold the channel receiver (digital only)
in reset during reconfiguration.
Related Information
• Model 1: Default Model
• Model 2: Acknowledgment Model
Send Feedback
pll_powerdown
, ,
rx_digitalreset tx_analogreset
,
rx_digitalreset
ports or use the channel soft register for digital and analog
,
tx_analogreset
on page 245
on page 254
for the fPLL through the soft registers
, and
, , and
tx_analogreset
tx_digitalreset
, and
rx_analogreset
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
rx_analogreset
,
ports or use the
327