Intel Cyclone 10 GX User Manual page 347

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
Port Name
reconfig_writedata[31:0]
reconfig_readdata[31:0]
reconfig_waitrequest
When Share reconfiguration interface is off, the Native PHY IP core provides an
independent reconfiguration interface for each channel. For example, when a
reconfiguration interface is not shared for a four-channel Native PHY IP instance,
reconfig_address[9:0]
channel 0,
bus of logical channel 1,
reconfiguration address bus of logical channel 2, and
correspond to the reconfiguration address bus of logical channel 3.
Table 192. Reconfiguration Interface Ports with Independent Native PHY
Reconfiguration Interfaces
The reconfiguration interface ports when Share reconfiguration interface is disabled. <N> represents the
number of channels.
Port Name
reconfig_clk[N-1:0]
reconfig_reset[N-1:0]
reconfig_write[N-1:0]
reconfig_read[N-1:0]
reconfig_address[N*10-1:0]
reconfig_writedata[N*32-1:0]
reconfig_readdata[N*32-1:0]
reconfig_waitrequest[N-1:0]
Send Feedback
Direction
Input
Output
Output
corresponds to the reconfiguration address bus of logical
reconfig_address[19:10]
reconfig_address[29:20]
Direction
Input
Input
Input
Input
Input
Input
Output
Output
Clock Domain
A 32-bit data write bus. Data to be written
reconfig_clk
into the address indicated by
reconfig_address
A 32-bit data read bus. Valid data is placed on
reconfig_clk
this bus after a read operation. Signal is valid
after
reconfig_waitrequest
then low.
A one-bit signal that indicates the Avalon
reconfig_clk
interface is busy. Keep the Avalon command
asserted until the interface is ready to proceed
with the read/write transfer. The behavior of
this signal depends on whether the feature
Separate reconfig_waitrequest from the
status of AVMM arbitration with PreSICE
is enabled or not. For more details, refer to
the Arbitration section.
correspond to the reconfiguration address
corresponds to the
reconfig_address[39:30]
Clock Domain
N/A Avalon clock for each channel. The clock
frequency is 100-125 MHz.
Resets the Avalon interface for each channel.
reconfig_clk
Asynchronous to assertion and synchronous to
deassertion.
Write enable signal for each channel. Signal is
reconfig_clk
active high.
Read enable signal for each channel. Signal is
reconfig_clk
active high.
A 10-bit address bus for each channel.
reconfig_clk
A 32-bit data write bus for each channel. Data
reconfig_clk
to be written into the address indicated by the
corresponding address field in
reconfig_address
A 32-bit data read bus for each channel. Valid
reconfig_clk
data is placed on this bus after a read
operation. Signal is valid after
goes high and then low.
A one-bit signal for each channel that
reconfig_clk
indicates the Avalon interface is busy. Keep
the Avalon command asserted until the
interface is ready to proceed with the read/
®
Intel Cyclone
Description
.
goes high and
Description
.
waitrequest
continued...
®
10 GX Transceiver PHY User Guide
347