Intel Cyclone 10 GX User Manual page 370

Figure 220. Using Multiple Reconfiguration Profiles
To enable the Quartus Prime software to close timing more accurately in this example,
the following constraints must be created:
•
create_clock -name tx_clkout_enh -period 5.12 [get_pins
{native_inst|xcvr_native_c10_0|
g_xcvr_native_insts[0].twentynm_xcvr_native_inst|
twentynm_xcvr_native_inst|inst_twentynm_pcs|
gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_p
ld_pcs_interface|pld_pcs_tx_clk_out}] -add
This constraint creates the
in the FPGA fabric.
•
create_clock -name rx_clkout_enh –period 5.12 [get_pins
{native_inst|xcvr_native_c10_0|
g_xcvr_native_insts[0].twentynm_xcvr_native_inst|
twentynm_xcvr_native_inst|inst_twentynm_pcs|
gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_p
ld_pcs_interface|pld_pcs_rx_clk_out}] -add
This constraint creates the
in the FPGA fabric.
•
set_false_path -from [get_clocks {tx_clkout_enh}] -to
[get_registers <Core Logic A>]
Based on how the clocks are connected in the design, you might have to include
additional constraints to set false paths from the registers in the core logic to the
clocks.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
370
6. Reconfiguration Interface and Dynamic Reconfiguration
FPGA Fabric
tx_clkout
Core Logic (A)
for Standard
PCS
Core Logic (B)
for Enhanced
rx_clkout
PCS
tx_clkout
rx_clkout
UG-20070 | 2018.09.24
Transceiver Channel
Transmitter (TX)
Receiver (RX)
clock that is used to clock the core logic B
clock that is used to clock the core logic B
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