How To Implement Cpri In Cyclone 10 Gx Transceivers - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
rx_std_wa_patternalign
even when it finds the alignment pattern in a new word boundary. When the word
aligner is synchronized to the new word boundary,
rx_syncstatus
PCS-PMA Width =20
When the PMA-PCS width is 20, any alignment pattern found after the initial alignment
in a different word boundary causes the word aligner to resynchronize to this new
word boundary on the rising edge of
rx_std_wa_patternalign
current word boundary until the next rising edge of
When the word aligner is synchronized to the new word boundary,
rx_patterndetect
remain asserted until the next rising edge of
Figure 73. Word Aligner in Manual Alignment Mode Waveform
rx_std_wa_patternalign
rx_parallel_data
rx_patterndetect
Related Information
Word Aligner

2.8.4. How to Implement CPRI in Cyclone 10 GX Transceivers

You should be familiar with the Standard PCS and PMA architecture, PLL architecture,
and the reset controller before implementing your CPRI protocol.
1. Instantiate the Cyclone 10 Transceiver Native PHY IP from the IP Catalog.
Refer to
2. Select CPRI (Auto) or CPRI (Manual) from the Transceiver configuration
rules list located under Datapath Options, depending on which protocol you are
implementing.
3. Use the parameter values in the tables in
CPRI
described in
your specific requirements.
4. Click Generate to generate the Native PHY IP (this is your RTL file).
Send Feedback
, the word aligner maintains the current word boundary
are asserted for one parallel clock cycle.
is edge sensitive. The word aligner will maintain the
will assert for one parallel clock cycle and rx_syncstatus will
rx_clkout
0... f1e4b6e4 b9dbf1db 915d061d e13f913f
0
rx_syncstatus 0000
on page 305
Select and Instantiate the PHY IP Core
on page 155 as a starting point. Or, you can use the protocol presets
Preset Configuration
rx_patterndetect
rx_std_wa_patternalign
rx_std_wa_patternalign
rx_std_wa_patternalign
7a4ae24a bcbc7b78 bcbcbcbc
1100 1111
1100 1111
on page 17 for more details.
Native PHY IP Parameter Settings for
Options. You can then modify the setting to meet
® ®
Intel Cyclone
and
;
.
.
95cd3c50 91c295cd ded691c2
0000
10 GX Transceiver PHY User Guide
153