Intel Cyclone 10 GX User Manual page 223

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
The steps below explain the x6/xN bonding process:
1. The ATX PLL or the fPLL generates a high speed serial clock.
2. The PLL drives the high speed serial clock to the master CGB via the x1 clock
network.
3. The master CGB drives the high speed serial and the low speed parallel clock into
the x6 clock network.
4. The x6 clock network feeds the TX clock multiplexer for the transceiver channels
within the same transceiver bank. The local CGB in each transceiver channel is
bypassed.
5. To drive the channels in adjacent transceiver banks, the x6 clock network drives
the xN clock network. The xN clock network feeds the TX clock mutiplexer for the
transceiver channels in these adjacent transceiver banks.
Related Information
• xN Clock Lines
• Cyclone 10 GX Device Datasheet
3.9.1.2. PLL Feedback Compensation Bonding
In PLL feedback compensation bonding, channels are divided into bonded groups
based on physical location with a four-channel or six-channel transceiver bank. All
channels within the same six-channel transceiver bank are assigned to the same
bonded group.
In PLL feedback compensation bonding, each bonded group is driven by its own set of
high-speed serial and low-speed parallel clocks. Each bonded group has its own PLL
and master CGB. To maintain the same phase relationship, the PLL and master CGB
for different groups share the same reference clocks.
The steps below explain the PLL feedback compensation bonding process:
1. The same input reference clock drives the local PLL in each three-channel or six-
channel transceiver bank.
2. The local PLL for the bonding group drives the master CGB.
3. The master CGB feeds the x6 clock lines. The master CGB drives the transceiver
channels in the bonding group via the x6 clock network.
4. The parallel output of the master CGB is the feedback input to the PLL.
5. In this mode, all channels are phase aligned to the same input reference clock.
PLL Feedback Compensation Bonding Advantages over x6/xN Bonding Mode
• There is no data rate restriction. The x6 clock network used for PLL feedback
compensation bonding can run up to the maximum data rate of the device used.
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Intel Cyclone 10 GX Transceiver PHY User Guide
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