Intel Cyclone 10 GX User Manual page 304

tx_dispval
corresponds to the LSByte of the input data and the MSB corresponds to the MSByte
of the input data.
5.3.1.3.5. 8B/10B Encoder Bit Reversal Feature
Figure 200. 8B/10B Encoder Bit Reversal Feature
7
The bit reversal feature reverses the order of the bits of the input data. Bit reversal is
performed at the output of the 8B/10B Encoder and is available even when the
8B/10B Encoder is disabled. For example, if the input data is 20-bits wide, bit reversal
switches bit [0] with bit [19], bit [1] with bit [18] and so on.
5.3.1.3.6. 8B/10B Encoder Byte Reversal Feature
Figure 201. 8B/10B Encoder Byte Reversal Feature
8
The byte reversal feature is available only when the PCS-PMA interface width is 16 bits
or 20 bits. Byte reversal is performed at the output of the 8B/10B Encoder and is
available even when the 8B/10B Encoder is disabled. This feature swaps the LSByte
with the MSByte. For example, when the PCS-PMA interface width is 16-bits, [7:0] bits
(LSByte) gets swapped with [15:8] bits (MSByte).
5.3.1.4. Polarity Inversion Feature
The polarity inversion feature is used in situations where the positive and the negative
signals of a serial differential link are erroneously swapped during board layout. You
can control this feature through
Polarity Inversion option under the Standard PCS tab of the Native PHY IP Core. The
polarity inversion feature inverts the value of each bit of the input data. For example,
if the input data is 00101001, then the data gets changed to 11010110 after polarity
inversion.
5.3.1.5. Pseudo-Random Binary Sequence (PRBS) Generator
Note: Refer to the PRBS Generator section in the Enhanced PCS Architecture chapter.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
304
are two bits each. The LSB of
0
B A
15 0 7
5. Cyclone 10 GX Transceiver PHY Architecture
tx_forcedisp
Output Input
Bit Reversal Mode
Data Data
(8B/10B Encoder)
Input
Output Byte Reversal Mode
Data
Data (8B/10B Encoder)
, by enabling the Enable TX
tx_polinv port
UG-20070 | 2018.09.24
and
tx_dispval
0 7
A B
0 7 8 15
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