Intel Cyclone 10 GX User Manual page 307

5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
The PCS performs pattern detection on the incoming data from the PMA. The PCS
aligns the data, after it indicates to the PMA the number of serial bits to clock slip the
boundary.
If the incoming data has to be realigned,
reasserted to initiate another pattern alignment. Asserting
rx_std_wa_patternalign
already achieved. This may cause
Table 172. PCS-PMA Interface Widths and Protocol Implementations
PCS-PMA Interface Width
8
10
16
20
5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes
Table 173. Word Aligner Pattern Length for Various Word Aligner Modes
PCS-PMA Supported Word
Interface Aligner Modes
Width
8 Bit slip
Manual
10 Bit slip
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can cause the word align to lose synchronization if
rx_syncstatus
Basic
• Basic
• Basic rate match
• CPRI
• PCIe Gen1 and Gen2
• GigE
Basic
• CPRI
• Basic
• Basic rate match
Supported
rx_std_wa_patte
Word Aligner
rnalign
Pattern
Lengths
8
rx_std_wa_patt
ernalign
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
8, 16 Word alignment is
controlled by
rx_std_wa_patt
ernalign
edge-sensitive to
this signal.
7
rx_std_wa_patt
ernalign
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
rx_std_wa_patternalign
to go low.
Protocol Implementations
rx_syncstatus
behavior
behavior
N/A
has no
Asserted high for
one parallel clock
cycle when the
word aligner aligns
and is
to a new boundary.
N/A
has no
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Intel Cyclone 10 GX Transceiver PHY User Guide
must be
rx_patterndetect
behavior
N/A
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
N/A
continued...
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