User Recalibration Sequence - Intel Cyclone 10 GX User Manual

You can initiate the recalibration process by writing to the specific recalibration
registers. You must also reset the transceivers after performing user recalibration. For
example, if you perform data rate auto-negotiation that involves PLL reconfiguration,
and PLL and channel interface switching, then you must reset the transceivers.
The proper reset sequence is required after calibration. Intel recommends you use the
Transceiver PHY Reset Controller IP which has
inputs and follow Intel's recommended reset sequence. You need to connect
tx_cal_busy
controller inputs in your design. Reset upon calibration is automatically processed
when you perform user recalibration.
Related Information
• Implementing PLL Cascading
• Implementing PLL Feedback Compensation Bonding Mode
• Recommended Reset Sequence
• Transmit PLLs Spacing Guidelines when using ATX PLLs and fPLLs

7.4.2. User Recalibration Sequence

Figure 224. User Recalibration Sequence for ATX PLL, fPLL and Native PHY IP (RX PMA /
TX PMA)
User recalibration requires access to the internal configuration bus and calibration
registers through the Avalon-MM reconfiguration interface. Follow the recalibration
example steps detailed in Calibration Example to perform a user recalibration process
for each ATX PLL IP, fPLL IP and Native PHY IP (RX PMA / TX PMA).
Related Information
Calibration Example
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
384
and from the Native PHY IP core outputs to the reset
rx_cal_busy
on page 240
on page 246
ATX PLL Calibration
fPLL Calibration
PMA RX
Calibration (1)
PMA TX
Calibration (2)
Calibration
Done
Note:
(1) If you are using the CDR/CMU PLL, you need to trigger RX
PMA recalibration.
(2) If you are using the CMU PLL as TX PLL, you need to trigger
RX PMA recalibration followed by a TX PMA recalibration.
on page 385
UG-20070 | 2018.09.24
and
tx_cal_busy rx_cal_busy
on page 237
7. Calibration
on page 200
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