Intel Cyclone 10 GX User Manual page 297

5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
For example, after frame lock is achieved, data is written after the first alignment
word (SYNC word) is found on that channel. As a result,
partially empty flag ) of that channel goes low. You must monitor the
rx_enh_fifo_pempty
rx_enh_fifo_pempty
rx_enh_fifo_pfull
all lanes of the link, you start reading from all the FIFOs by asserting
rx_enh_fifo_rd_en
goes high before a
reset the FIFO by toggling the
process.
Figure 191. RX FIFO as Interlaken Deskew FIFO
5.2.2.10.4. 10GBASE-R Mode
In 10GBASE-R mode, the RX FIFO operates as a clock compensation FIFO. When the
block synchronizer achieves block lock, data is sent through the FIFO. Idle ordered
sets (OS) are deleted and Idles are inserted to compensate for the clock difference
between the RX low speed parallel clock and the FPGA fabric clock (±100 ppm for a
maximum packet length of 64,000 bytes).
Idle OS Deletion
Deletion of Idles occurs in groups of four OS (when there are two consecutive OS)
until the
(LW) and an upper word (UW)—is checked for whether it can be deleted by looking at
both the current and previous words.
For example, the current LW can be deleted if it is Idle and the previous UW is not a
Terminate.
Table 169. Conditions Under Which a Word Can be Deleted
In this table X=don't care, T=Terminate, I=Idle, and OS=order set.
Deletable Case
Lower Word
Send Feedback
and
rx_enh_fifo_pfull
flags from all channels deassert before any
flag asserts, which implies alignment word has been found on
. Otherwise, if a
rx_enh_fifo_pempty
rx_enh_fifo_align_clr
FPGA Fabric Interface
rx_enh_fifo_align_clr
rx_enh_fifo_rd_en
User
Deskew
FSM
rx_enh_fifo_pfull
Word
1 UW
LW
2 UW
flags of all channels. If
rx_enh_fifo_pfull
flag deassertion on all channels, you must
rx_enh_fifo_pempty
rx_enh_fifo_pfull
flag deasserts. Every word—consisting of a lower word
Previous Current
!T X
X I
OS X
®
Intel Cyclone
rx_enh_fifo_pempty
flag from any channel
signal and repeating the
RX FIFO
Output
!T X
X X
OS X
continued...
®
10 GX Transceiver PHY User Guide
(FIFO
297