Intel Cyclone 10 GX User Manual page 159

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 76. Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS)
Configuration
Notes:
1. Can be enabled or disabled based on the gearbox ratio selected
2. Depends on the value of the clock division factor chosen
3. To use the Scrambler and Descrambler, you must use a 66:32, 66:40, or 66:64 gear ratio and the Block Synchronizer must be enabled
2.9.1.1. How to Implement the Basic (Enhanced PCS) Transceiver Configuration
Rules in Cyclone 10 GX Transceivers
You should be familiar with the Basic (Enhanced PCS) and PMA architecture, PLL
architecture, and the reset controller before implementing the Basic (Enhanced PCS)
Transceiver Configuration Rule.
1. Open the IP Catalog and select the Cyclone 10 GX Transceiver Native PHY IP.
Refer to
2. Select Basic (Enhanced PCS) from the Transceiver Configuration Rules list
located under Datapath Options.
3. Use the parameter values in the tables in
Basic (Enhanced PCS) Transceiver Configuration Rules
can use the protocol presets described in
then modify the settings to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
Send Feedback
Transmitter PMA Transmitter Enhanced PCS
32
32
PRBS
Generator
Receiver PMA Receiver Enhanced PCS
32
32
PRBS
Verifier
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Select and Instantiate the PHY IP Core
PRP
Generator
Parallel Clock (322.265625 MHz)
tx_pma_div_clkout
rx_pma_div_clkout
PRP
Verifier
Parallel Clock (322.265625 MHz)
10GBASE-R
BER Checker
(5156.25 MHz) =
Data rate/2 (2)
Clock Divider
Serial Clock
Parallel and Serial Clocks
on page 17 for more details.
Transceiver Native PHY IP Parameters for
as a starting point. Or, you
Transceiver Native PHY
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
FPGA
Fabric
32-bit
data
tx_clkout
32-bit
data
rx_clkout
ATX PLL
fPLL
CMU PLL
Input Reference Clock
Presets. You can
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