Intel Cyclone 10 GX User Manual page 12

A PMA is the transceiver's electrical interface to the physical medium. The transceiver
PMA consists of standard blocks such as:
• serializer/deserializer (SERDES)
• clock and data recovery PLL
• analog front end transmit drivers
• analog front end receive buffers
The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS
blocks are fed by multiple clock networks driven by high performance PLLs. In PCS
Direct configuration, the data flow is through the PCS block, but all the internal PCS
blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA
fabric.
1.2.2.1. The Transceiver Channel
Figure 6. Transceiver Channel in Full Duplex Mode
Notes:
(1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.
Intel Cyclone 10 GX transceiver channels have three types of PCS blocks that together
support continuous data rates between 1.0 Gbps and 10.81344 Gbps.
Table 2. PCS Types Supported by Transceiver Channels
PCS Type
Standard PCS
Enhanced PCS
PCS Direct
Note: The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver.
For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the
transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied
at the receiver.
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Intel Cyclone 10 GX Transceiver PHY User Guide
12
Transmitter PMA
(1)
Serializer
Receiver PMA
(1)
CDR Deserializer
1.0 Gbps to 10.81344 Gbps
1.0 Gbps to 12.5 Gbps
1.0 Gbps to 12.5 Gbps
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1. Intel Cyclone 10 GX Transceiver PHY Overview
Transmitter PCS
Standard PCS
Enhanced PCS
PCS Direct
Receiver PCS
Standard PCS
Enhanced PCS
PCS Direct
Data Rate
UG-20070 | 2018.09.24
FPGA Fabric
(1)
Soft PIPE Hard IP
(Optional)
(Optional)
(1)
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