Intel Cyclone 10 GX User Manual page 136

Parameter
Enable manual counter configuration
Enable ATX to fPLL cascade clock input
port
Settings
Bandwidth
Feedback
Operation mode
Output frequency
Transceiver usage
PLL output frequency
PLL datarate
PLL integer reference clock frequency
Master Clock Generation Block (MCGB)
Include master clock generation block
Clock division factor
Enable x6/xN non-bonded high-speed
clock output port
Enable PCIe clock switch interface
Number of auxiliary MCGB clock input
ports
MCGB input clock frequency
MCGB output data rate
Bonding
Enable bonding clock output ports
Enable feedback compensation bonding
PMA interface width
Dynamic Reconfiguration
Enable dynamic reconfiguration
Enable Altera Debug Master Endpoint
Separate avmm_busy from
reconfig_waitrequest
Optional Reconfiguration Logic
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
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Intel Cyclone 10 GX Transceiver PHY User Guide
136
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Gen1 PIPE
Disable
Disable
Low, Medium, High
Direct
1250MHz
2500Mbps
100 MHz, 125 MHZ
Disable for x1
Enable for x2, x4
N/A for x1
1 for x2, x4
N/A for x1
Disable for x2, x4
N/A for x1
Disable for x2, x4
N/A for x1
0 for x2, x4
1250MHz
2500Mbps
N/A for x1 design
Enable for x2, x4
N/A for x1 design
Disable for x2, x4
N/A for x1 design
10 for x2, x4
Disable
Disable
N/A
N/A
N/A
N/A
UG-20070 | 2018.09.24
Gen2 PIPE
Disable
Disable
Low, Medium, High
Direct
2500MHz
5000Mbps
100 MHz, 125 MHZ
Disable for x1
Enable for x2, x4
N/A for x1
1 for x2, x4
N/A for x1
Disable for x2, x4
N/A for x1
Enable for x2, x4
N/A for x1
0 for x2, x4
2500MHz
5000Mbps
N/A for x1 design
Enable for x2, x4
N/A for x1 design
Disable for x2, x4
N/A for x1 design
10 for x2, x4
Disable
Disable
N/A
N/A
N/A
N/A
continued...
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