Fpll Ports For Pipe - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Table 127. Bit Mappings When the Simplified Interface Is Disabled
This section contains the recommended settings for this protocol. Refer to Using the Cyclone 10 GX Transceiver
Native PHY IP Core for the full range of parameter values.
Signal Name
tx_parallel_data
tx_datak
pipe_tx_compliance
pipe_tx_elecidle
pipe_tx_detectrx_loopbacK
pipe_powerdown
pipe_tx_margin
pipe_tx_swing
rx_parallel_data
rx_datak
rx_syncstatus
pipe_phy_status
pipe_rx_valid
pipe_rx_status
pipe_tx_deemph
Refer to section 6.6 of Intel PHY Interface for PCI Express (PIPE) Architecture for more
information.
Related Information
• Intel PHY Interface for PCI Express (PIPE) Architecture
• Bit Mappings When the Simplified Interface is Disabled
• Using the Cyclone 10 GX Transceiver Native PHY IP Core

2.7.9. fPLL Ports for PIPE

Table 128. fPLL Ports for PIPE
This section contains the recommended settings for this protocol. Refer to Using the Cyclone 10 GX Transceiver
Native PHY IP Core for the full range of parameter settings.
Port
Pll_powerdown
Pll_reflck0
Send Feedback
Gen1 (TX Byte Serializer and
RX Byte Deserializer disabled)
tx_parallel_data[7:0]
tx_parallel_data[8]
tx_parallel_data[9]
tx_parallel_data[10]
tx_parallel_data[46]
tx_parallel_data[48:47]
tx_parallel_data[51:49]
tx_parallel_data[53]
rx_parallel_data[7:0]
rx_parallel_data[8]
rx_parallel_data[10]
rx_parallel_data[65]
rx_parallel_data[66]
rx_parallel_data[69:67]
Direction Clock Domain
Input Asynchronous Resets the PLL when asserted high. Needs to be connected to
the Transceiver PHY Reset Controller
Input N/A Reference clock input port 0. There are five reference clock
input ports. The number of reference clock ports available
depends on the Number of PLL reference clocks parameter.
Gen1 (TX Byte Serializer and RX Byte
Deserializer in X2 mode), Gen2 (TX
Byte Serializer and RX Byte
Deserializer in X2 mode)
tx_parallel_data[29:22,7:0]
tx_parallel_data[30,8]
tx_parallel_data[31,9]
tx_parallel_data[32,10]
tx_parallel_data[46]
tx_parallel_data[48:47]
tx_parallel_data[51:49]
tx_parallel_data[53]
rx_parallel_data[39:32,7:0]
rx_parallel_data[40,8]
rx_parallel_data[42,10]
rx_parallel_data[65]
rx_parallel_data[66]
rx_parallel_data[69:67]
N/A
tx_parallel_data[52]
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Description
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Intel Cyclone 10 GX Transceiver PHY User Guide
output.
pll_powerdown
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