Intel Cyclone 10 GX User Manual page 184

Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
RX rate match FIFO mode
RX rate match insert/delete -ve pattern (hex)
RX rate match insert/delete +ve pattern (hex)
Enable rx_std_rmfifo_full port
Enable rx_std_rmfifo_empty port
Enable TX bit slip
Enable tx_std_bitslipboundarysel port
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Number of word alignment patterns to achieve sync
Number of invalid data words to lose sync
Number of valid data words to decrement error count
Enable fast sync status reporting for deterministic latency SM
Enable rx_std_wa_patternalign port
Enable rx_std_wa_a1a2size port
Enable rx_std_bitslipboundarysel port
Enable rx_bitslip port
Enable TX bit reversal
Enable TX byte reversal
Enable TX polarity inversion
Enable tx_polinv port
Enable RX bit reversal
Enable rx_std_bitrev_ena port
Enable RX byte reversal
Enable rx_std_byterev_ena port
Enable RX polarity inversion
Enable rx_polinv port
Enable rx_std_signaldetect port
Enable PCIe dynamic datarate switch ports
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Intel Cyclone 10 GX Transceiver PHY User Guide
184
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Parameter
UG-20070 | 2018.09.24
Range
On/Off
On/Off
Disabled
Basic 10-bit PMA (for Basic with Rate Match)
Basic 20-bit PMA (for Basic with Rate Match)
User-defined value
User-defined value
On/Off
On/Off
On/Off
On/Off
bitslip
manual (PLD controlled)
synchronous state machine
7, 8, 10, 16, 20, 32, 40
User-defined value
0-255
0-63
0-255
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Off
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