Intel Cyclone 10 GX User Manual page 126

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For INSERT/DELETE cases: The flag status appears on the COM symbol of the SKP
ordered set where insertion or deletion occurs.
For FULL/EMPTY cases: The flag status appears where the character is inserted or
deleted.
Note: When the PIPE interface is on, it translates the value of the flag to the
The PIPE mode also has a "0 ppm" configuration option that you can use in
synchronous systems. The Rate Match FIFO Block is not expected to do any clock
compensation in this configuration, but latency will be minimized.
Figure 58.
Rate Match Deletion
This figure shows an example of rate match deletion in the case where two /K28.0/ SKP symbols must be
deleted. Only one /K28.0/ SKP symbol is deleted per SKP ordered set received.
rmfifo_input_data
rx_parallel_data
pipe_rx_status[2:0]
Figure 59.
Rate Match Insertion
The figure below shows an example of rate match insertion in the case where two SKP symbols must be
inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received.
rmfifo_input_data
rx_parallel_data
pipe_rx_status[2:0]
Figure 60.
Rate Match FIFO Full
The rate match FIFO in PIPE mode automatically deletes the data byte that causes the FIFO to go full and
drives
pipe_rx_status[2:0]
the rate match FIFO full condition in PIPE mode. The rate match FIFO becomes full after receiving data byte
D4.
tx_parallel_data
rx_parallel_data
pipe_rx_status[2:0]
®
®
Intel
Cyclone
10 GX Transceiver PHY User Guide
126
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
appropriate
pipe_rx_status[2:0]
First SKP Ordered Set
K28.5
K28.0
Dx.y
K28.5
Dx.y
K28.5
3'b010
xxx
3'b010
First SKP Ordered Set
K28.5
K28.0
Dx.y
K28.5
K28.0
K28.0
3'b001
xxx
xxx
= 3'b101 synchronous to the subsequent data byte. The figure below shows
D1
D2
D3
D1
D2
D3
xxx
xxx
xxx
signal.
SKP Symbol
Deleted
Second SKP Ordered Set
K28.5
K28.0
K28.0
Dx.y
K28.0
K28.0
xxx
xxx
xxx
Second SKP Ordered Set
K28.5
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
xxx
3'b001
xxx
xxx
SKP Symbol Inserted
D4
D5
D6
D7
D4
D6
xxx
3'b101
xxx
UG-20070 | 2018.09.24
Dx.y
K28.0
K28.0
K28.0
K28.0
K28.0
xxx
xxx
xxx
D7
D8
D8
xx
xx
xx
xxx
xxx
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