Intel Cyclone 10 GX User Manual page 280

Related Information
• Analog Parameter Settings
• Intel Cyclone 10 GX Register Map
5.1.2.2. Clock Data Recovery (CDR) Unit
The PMA of each channel includes a channel PLL that you can configure as a receiver
clock data recovery (CDR) for the receiver. You can also configure the channel PLL of
channels 1 and 4 as a clock multiplier unit (CMU) PLL for the transmitter in the same
bank.
Figure 175. Channel PLL Configured as CDR
rx_serial_data
Note:
1. The Quartus® Prime Pro Edition software automatically chooses the optimal values.
5.1.2.2.1. Lock-to-Reference Mode
In LTR mode, the phase frequency detector (PFD) in the CDR tracks the receiver input
reference clock. The PFD controls the charge pump that tunes the VCO in the CDR.
The
rx_is_lockedtoref
CDR has locked to the phase and frequency of the receiver input reference clock.
Note: The phase detector (PD) is inactive in LTR mode.
5.1.2.2.2. Lock-to-Data Mode
During normal operation, the CDR must be in LTD mode to recover the clock from the
incoming serial data. In LTD mode, the PD in the CDR tracks the incoming serial data
at the receiver input. Depending on the phase difference between the incoming data
and the CDR output clock, the PD controls the CDR charge pump that tunes the VCO.
Note:
The PFD is inactive in LTD mode. The
randomly and is not significant in LTD mode.
After switching to LTD mode, the
The actual lock time depends on the transition density of the incoming data and the
parts per million (ppm) difference between the receiver input reference clock and the
upstream transmitter reference clock. The
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
280
on page 388
Channel PLL
LTR/LTD
Controller
Phase
Detector
(PD)
N
Phase
refclk
Divider
Frequency
(1)
Detector
(PFD)
status signal is asserted active high to indicate that the
5. Cyclone 10 GX Transceiver PHY Architecture
Down
Up
Charge Pump
&
Loop Filter
Up
Down
rx_is_lockedtoref
rx_is_lockedtodata
rx_is_lockedtodata
UG-20070 | 2018.09.24
rx_is_lockedtodata
Recovered Clock
/2
Voltage
L
Controlled
Divider
Serial Clock
Oscillator
(1)
(VCO)
Lock
rx_is_lockedtoref
Detect
M
Divider
(1)
status signal toggles
status signal is asserted.
signal toggles until
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