Intel Cyclone 10 GX User Manual page 183

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Table 149. RX PMA Parameters
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port
rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
Table 150. Standard PCS Parameters
Standard PCS / PMA interface width
FPGA fabric / Standard TX PCS interface width
FPGA fabric / Standard RX PCS interface width
Enable 'Standard PCS' low latency mode
TX FIFO mode
RX FIFO Mode
Enable tx_std_pcfifo_full port
Enable tx_std_pcfifo_empty port
Enable rx_std_pcfifo_full port
Enable rx_std_pcfifo_empty port
TX byte serializer mode
RX byte deserializer mode
Enable TX 8B/10B encoder
Send Feedback
Parameter
Parameter
Range
1, 2, 3, 4, 5
0, 1, 2, 3, 4
Legal range defined by Quartus Prime software
100, 300, 500, 1000
manual
On/Off
On/Off
Disabled, 1, 2, 33, 40, 50, 66
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Range
8, 10, 16, 20
8, 10, 16, 20, 32, 40
8, 10, 16, 20, 32, 40
On/Off
Off (for Basic with Rate Match)
low_latency
register_fifo
fast_register
low_latency
register_fifo
On/Off
On/Off
On/Off
On/Off
Disabled
Serialize x2
Serialize x4
Disabled
Deserialize x2
Deserialize x4
On/Off
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Intel Cyclone 10 GX Transceiver PHY User Guide
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