Intel Cyclone 10 GX User Manual page 74

Figure 21. 10X12.5 Gbps xN Bonding
ATX PLL
Note: Intel Cyclone 10 GX devices have transceiver channels that can support data rates
up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6 Gbps
for backplane communication.
Related Information
• Implementing x6/xN Bonding Mode
For detailed information on xN bonding limitations
• Using PLLs and Clock Networks
For more information about implementing PLLs and clocks
2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State
Machine
The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken
elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port
signals are provided to the FPGA fabric. Connect these signals to the MAC layer as
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
74
Transceiver PLL
Instance (6.25 GHz)
Master
CGB
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
(10 Ch Bonded 12.5 Gbps)
Transceiver Bank 1
xN
Transceiver Bank 2
on page 236
on page 231
UG-20070 | 2018.09.24
Native PHY Instance
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
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