Intel Cyclone 10 GX User Manual page 147

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
The following figures show the default configurations:
Figure 67. x2 Configuration
Note: The physical channel 0 aligns with logical channel 0. The logical PCS Master Channel 1
is specified as Physical Channel 1.
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CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
1 CH1 Master CH
0 CH0 Data CH
Physical
Logical
Channel Channel
fPLL
Master
ATX
CGB
PLL
Transceiver bank
fPLL
Master
ATX
CGB
PLL
fPLL
Master
ATX
CGB
PLL
Transceiver bank
fPLL
Master
ATX
CGB
PLL
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
147