Intel Cyclone 10 GX User Manual page 156

Table 136. TX PMA Parameters
TX channel bonding mode
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port
tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable rx_seriallpbken port
Table 137. RX PMA Parameters
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port
rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
Table 138. Standard PCS Parameters
Standard PCS / PMA interface width
FPGA fabric / Standard TX PCS interface width
FPGA fabric / Standard RX PCS interface width
Enable 'Standard PCS' low latency mode
TX FIFO mode
RX FIFO mode
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Intel Cyclone 10 GX Transceiver PHY User Guide
156
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Parameter
Parameter
Parameters
UG-20070 | 2018.09.24
Value
Not Bonded / PMA Bonding Only / PMA
and PCS Bonding
1
1
0
Off
On
2
Off
Off
Value
1
0
Select legal range defined by the Quartus Prime
software
1000
manual
Off
On
2
Off
On
On
Off
Off
Off
Value
20
32
32
Off
register_fifo
register_fifo
continued...
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