Intel Cyclone 10 GX User Manual page 157

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Enable tx_std_pcfifo_full port
Enable tx_std_pcfifo_empty port
Enable rx_std_pcfifo_full port
Enable rx_std_pcfifo_empty port
TX byte serializer mode
RX byte deserializer mode
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
RX rate match FIFO mode
RX rate match insert / delete -ve pattern (hex)
RX rate match insert / delete +ve pattern (hex)
Enable rx_std_rmfifo_full port
Enable rx_std_rmfifo_empty port
Enable TX bit slip
Enable tx_std_bitslipboundarysel port
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Number of word alignment patterns to achieve sync
Number of invalid data words to lose sync
Number of valid data words to decrement error count
Enable fast sync status reporting for deterministic latency SM
Enable rx_std_wa_patternalign port
Enable rx_std_wa_a1a2size port
Enable rx_std_bitslipboundarysel port
Enable rx_bitslip port
All options under Bit Reversal and Polarity Inversion
All options under PCIe Ports
(26)
These are unused when the transceiver PHY is in CPRI mode.
Send Feedback
Parameters Value
Off
Off
Off
Off
Serialize x2
Deserialize x2
On
Off
On
Disabled
0x00000000
0x00000000
Off
Off
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
deterministic latency (CPRI Auto
configuration)
manual (FPGA fabric controlled) (CPRI
Manual configuration)
10
0x000000000000017c
(26)
3
(26)
3
(26)
3
On / Off
On / Off
Off
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Off
Off
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
157