Intel Cyclone 10 GX User Manual page 306

5.3.2.1.2. Word Aligner Manual Mode
In manual alignment mode, the word aligner operation is controlled by
rx_std_wa_patternalign
sensitive to
width selected.
Table 171.
Word Aligner
PCS-PMA Interface Width
8
10
16
20
If
rx_std_wa_patternalign
programmed word alignment pattern in the received data stream. It updates the word
boundary if it finds the word alignment pattern in a new word boundary. If
rx_std_wa_patternalign
word boundary even when it sees the word alignment pattern in a new word
boundary.
The
rx_syncstatus
datapath, are forwarded to the FPGA fabric to indicate the word aligner status.
After receiving the first word alignment pattern after
asserted, both
parallel clock cycle. Any word alignment pattern received thereafter in the same word
boundary causes only
alignment pattern received thereafter in a different word boundary causes the word
aligner to re-align to the new word boundary only if
asserted. The word aligner asserts
whenever it re-aligns to the new word boundary.
5.3.2.1.3. Word Aligner Synchronous State Machine Mode
In synchronous state machine mode, when the programmed number of valid
synchronization code groups or ordered sets is received,
high to indicate that synchronization is acquired. The
constantly driven high until the programmed number of erroneous code groups is
received without receiving intermediate good groups, after which
driven low.
The word aligner indicates loss of synchronization (
until the programmed number of valid synchronization code groups are received
again.
5.3.2.1.4. Word Aligner Deterministic Latency Mode
In deterministic latency mode, the state machine removes the bit level latency
uncertainty. The deserializer of the PMA creates the bit level latency uncertainty as it
comes out of reset.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
306
. The word aligner operation is edge-sensitive or level-
rx_std_wa_patternalign
rx_std_wa_patternalign
is asserted, the word aligner looks for the
is deasserted, the word aligner maintains the current
and
rx_patterndetect
and
rx_syncstatus
rx_patterndetect
5. Cyclone 10 GX Transceiver PHY Architecture
, depending upon the PCS-PMA interface
Behavior
rx_std_wa_patternalign
Rising edge sensitive
Level sensitive
Rising edge sensitive
Rising edge sensitive
signals, with the same latency as the
rx_std_wa_patternalign
rx_patterndetect
to go high for one clock cycle. Any word
rx_std_wa_patternalign
for one parallel clock cycle
rx_syncstatus
rx_syncstatus
rx_syncstatus
rx_syncstatus
UG-20070 | 2018.09.24
Behavior
are driven high for one
is driven
signal is
rx_syncstatus
remains low)
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