Intel Cyclone 10 GX User Manual page 101

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
The protocol is applicable to systems communicating by local area networks including,
but not limited to, Ethernet. The protocol enables heterogeneous systems that include
clocks of various inherent precision, resolution, and stability to synchronize to a
grandmaster clock.
Figure 45. Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2
10.3125 Gbps
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R
The XGMII interface, specified by IEEE 802.3-2008, defines the 32-bit data and 4-bit
wide control character. These characters are clocked between the MAC/RS and the PCS
at both the positive and negative edge (double data rate – DDR) of the 156.25 MHz
interface clock.
The transceivers do not support the XGMII interface to the MAC/RS as defined in the
IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control
single data rate (SDR) interface between the MAC/RS and the PCS.
Send Feedback
Transmitter PMA Transmitter Enhanced PCS
40
PRBS
Generator
Parallel Clock
@ 257.8125 MHz (2)
Receiver PMA Receiver Enhanced PCS
40
66
PRBS
Verifier
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
64
66
PRP
Generator
tx_pma_div_clkout
rx_pma_div_clkout
64
PRP
Verifier
Parallel Clock
@ 257.8125 MHz (2)
10GBASE-R
BER Checker
Clock Divider
CMU PLL
Serial Clock
Parallel and Serial Clocks
Input Reference Clock
® ®
Intel Cyclone
FPGA
Fabric
64 (data) + 8 (control)
Soft Phase
Compensation
FIFO
TX XGMII
@ 156.25 MHz
tx_clkout
64 (data) + 8 (control)
Soft Clock
Compensation
FIFO
RX XGMII
@ 156.25 MHz
rx_clkout
ATX PLL
fPLL
10 GX Transceiver PHY User Guide
101