Reading From The Reconfiguration Interface; Writing To The Reconfiguration Interface - Intel Cyclone 10 GX User Manual

• Reconfiguration Interface and Arbitration with PreSICE Calibration Engine
373
• Avalon Interface Specifications

6.2.1. Reading from the Reconfiguration Interface

Reading from the reconfiguration interface of the Transceiver Native PHY IP core or
Transceiver PLL IP core retrieves the current value at a specific address. The dynamic
reconfiguration interface is compliant to the AVMM specifications.
Figure 209. Reading from the Reconfiguration Interface
reconfig_address
reconfig_read
reconfig_waitrequest
reconfig_readdata
reconfig_write
reconfig_writedata
1. The master asserts reconfig_address and reconfig_read after the rising edge of reconfig_clk.
2. The slave asserts reconfig_waitrequest, stalling the transfer.
3. The master samples reconfig_waitrequest. Because reconfig_waitrequest is asserted, the cycle becomes a wait state and reconfig_address,
reconfig_read, and reconfig_write remain constant.
4. The slave presents valid reconfig_readdata and deasserts reconfig_waitrequest.
5. The master samples reconfig_waitrequest and reconfig_readdata, completing the transfer.
After the
asserts for a few
the
reconfig_readdata
Note: You must check for the internal configuration bus arbitration before performing
reconfiguration. Refer to the Arbitration section for more details about requesting
access to and returning control of the internal configuration bus from PreSICE.
Related Information
Arbitration

6.2.2. Writing to the Reconfiguration Interface

Writing to the reconfiguration interface of the Transceiver Native PHY IP core or TX PLL
IP core changes the data value at a specific address. All writes to the reconfiguration
interface must be read-modify-writes, because two or more features may share the
same reconfiguration address. When two or more features share the same
reconfiguration address, one feature's data bits are interleaved with another feature's
data bits.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
318
1 3
reconfig_clk
2
signal is asserted, the
reconfig_read
reconfig_clock
bus contains valid data.
on page 325
6. Reconfiguration Interface and Dynamic Reconfiguration
119h
reconfig_waitrequest
cycles, then deasserts. This deassertion indicates
UG-20070 | 2018.09.24
on page
5
4
Valid readdata
signal
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