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Arria 10 SX Triple-rate SDI with Transceiver Toolkit
Reference Design User Guide
Date: 8/29/2017
Revision: 1.1
©2017 Intel Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, INTEL, MAX, MEGACORE, NIOS,
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Summary of Contents for Intel Arria 10 SX
- Page 1 Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
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Page 2: Table Of Contents
Table of Contents Introduction..............................3 Requirements ..............................3 Theory of Operation ............................5 How to Setup the Hardware for Link Test ..................... 8 How to Reconstruct and Running the Reference Design ................8 Conclusion..............................16 References ..............................16 Revision History ............................16... -
Page 3: Introduction
Introduction The objective of this design example is to demonstrate how to dynamically perform PMA analog settings tuning in a Triple-rate SDI link using transceiver toolkit. This design comes with SDI pattern generator up to 3G video mode which allow the loopback test from SDI TX to RX. It also equipped with In-System Source and Probe (ISSP) instance to allow real-time interface with the SDI link and for TRS and Frame lock monitoring. - Page 4 Figure 1. Arria 10 SoC Development Kit...
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Page 5: Theory Of Operation
Theory of Operation Figure 2. Block diagram of modules in the reference design Figure 2 shows the high-level modules in the reference design as well as the interfaces among the modules. The A10 transceiver Native PHY is used to configure and implement the hard transceiver channels. - Page 6 The following table shows the mapping of the sw[3..0] in the Spf_sample_design_ttk.spf to the video patterns: sw[3..0] Video Pattern 4'b0000 SD NTSC 4'b0001 SD PAL 4'b0010 HD 1080i60 4'b0011 HD 1080i50 4'b0100 HD 1080p24 4'b0101 HD 720p60 4'b0110 HD 720p30 4'b0111 HD 1080p30 4'b1000...
- Page 7 Transceiver toolkit is generally used to find the optimal PMA analog settings of the transceiver for a board setup. Transceiver toolkit comes with user interface to allow user to real time interface through with the transceiver as well as dynamically change the PMA analog settings on-the-fly by just clicking buttons.
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Page 8: How To Setup The Hardware For Link Test
Figure 5. Board Setup for SDI Link Loopback Test How to Setup the Hardware for Link Test Follow these steps to setup the hardware to run the reference design: 1. Connect the FPGA Mezzanine Card (FMC) to High Speed Mezzanine Card (HSMC) adapter board to FMC B daughtercard port of the Arria 10 SoC Development Kit 2. - Page 9 c. Replace ".source_export ({reconfig_rst, ISSP_sw[3:0]}), // source.export" with ".source_export ({sdi_clk_sel,reconfig_rst, ISSP_sw[3:0]}), // source.export" in the a10_top.v d. Add “set_location_assignment PIN_AL22 -to si516_fs” to a10_top.qsf 3. Perform full compilation with the design 4. Program the SOF file generated into the Arria 10 SoC Development Kit 5.
- Page 10 22. If require, you may then further manually fine tune by using the values found by transceiver toolkit as starting points Figure 6. The rx_frame_locked and rx_trs_locked Signals Assert after Successful Locking to the 3G SDI Signal...
- Page 11 Figure 7. Loading SOF File in Transceiver Toolkit...
- Page 12 Figure 8. Establish Control to the Transceiver Link...
- Page 13 Figure 9. Dynamically Change the TX VOD Settings Figure 10. Hold the SDI RX Transceiver Rate Change...
- Page 14 Figure 11. Transceiver Toolkit Auto Sweep for a VOD Range...
- Page 15 Figure 12. Optimal Setting by Transceiver Toolkit Auto Sweep...
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Page 16: Conclusion
Conclusion The design example provides a reference on how to dynamically perform PMA analog settings tuning in a Triple-rate SDI link using transceiver toolkit. References • Triple-Rate SDI II Simple Design http://www.alterawiki.com/wiki/Triple-Rate_SDI_II_Simple_Design • SDI II IP Core User Guide https://www.altera.com/documentation/bhc1410937441525.html •...
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