Intel Cyclone 10 GX User Manual page 105

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Table 91. RX PMA Parameters
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
Table 92. Enhanced PCS Parameters
Enhanced PCS/PMA interface width
FPGA fabric/Enhanced PCS interface width
Enable Enhanced PCS low latency mode
Enable RX/TX FIFO double-width mode
TX FIFO mode
TX FIFO partially full threshold
TX FIFO partially empty threshold
RX FIFO mode
RX FIFO partially full threshold
RX FIFO partially empty threshold
Table 93. 64B/66B Encoder and Decoder Parameters
Enable TX 64B/66B encoder
Enable RX 64B/66B decoder
Enable TX sync header error insertion
Table 94. Scrambler and Descrambler Parameters
Enable TX scrambler (10GBASE-R / Interlaken)
TX scrambler seed (10GBASE-R / Interlaken)
Enable RX descrambler (10GBASE-R / Interlaken)
Send Feedback
Parameter
Parameter
Parameter
Parameter
Range
1 to 5
0 to 4
322.265625 MHz and 644.53125 MHz
100, 300, 500, 1000
manual
Range
32, 40, 64
66
On
Off
Off
• Phase Compensation (10GBASE-R)
• Register or Fast register (10GBASE-R with 1588)
11
2
• 10GBASE-R (10GBASE-R)
• Register (10GBASE-R with 1588)
23
2
Range
On
On
On
Off
Range
On
0x03ffffffffffffff
On
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
105