Intel Cyclone 10 GX User Manual page 133

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Table 122. Parameters for Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes - RX
PMA
This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX
Transceiver Native PHY IP Core for the full range of parameter values.
RX CDR Options
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
Equalization
CTLE adaptation mode
DFE adaptation mode
Number of fixed dfe taps
RX PMA Optional Ports
Enable
rx_analog_reset_ack
Enable
rx_pma_clkout
Enable
rx_pma_div_clkout
division factor
rx_pma_div_clkout
Enable
rx_pma_clkslip
Enable
rx_is_lockedtodata
Enable
rx_is_lockedtoref
Enable
rx_set_locktodata
ports
rx_set_locktoref
Enable
rx_seriallpbken
Enable PRBS Verifier Control and Status ports
Table 123. Parameters for Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes -
Standard PCS
This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter
Standard PCS configurations
Standard PCS / PMA interface width
FPGA Fabric / Standard TX PCS interface width
FPGA Fabric / Standard RX PCS interface width
Enable Standard PCS low latency mode
Standard PCS FIFO
TX FIFO mode
Send Feedback
port
port
port
port
port
port
and
port
Gen1 PIPE
1
0
100, 125 MHz
1000
Manual
Disabled
NA
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Gen1 PIPE
10
8, 16
8, 16
Off
low_latency
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
Gen2 PIPE
1
0
100, 125 MHz
1000
Manual
Disabled
NA
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Gen2 PIPE
10
16
16
Off
low_latency
continued...
133